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rev. 0 a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 ADV7185 professional ntsc/pal video decoder with 10-bit ccir656 output adllt is a trademark and adv is a registered trademark of analog devices, inc. features analog video to digital ycrcb video decoder: ntsc-(m/n), pal-(b/d/g/h/i/m/n) adv ? 7185 integrates two 12-bit adcs clocked from a single 27 mhz crystal dual video clocking schemes: line-locked clock compatible (llc) adaptive digital line length tracking (adllt?) 3-line chroma comb filter real-time clock and status information output integrated agc (automatic gain control) and clamping multiple programmable analog input formats: cvbs (composite video) svhs (y/c) ycrcb component (vesa, mii, smpte, and betacam) 6 analog input video channels real-time horizontal and vertical scaling automatic ntsc/pal identification differential mode video input functional block diagram iso refout ain1 ain2 ain3 ain4 ain5 ain6 analog i/p multiplexing automa tic gain control (agc ) clamp and dc restore 12-bit adc luma antialias lpf shaping and notch lpf peaking hpf/lpf resampling and horizontal scaling sync detection ADV7185 resampling and horizontal scaling chroma antialias lpf shaping lpf switch luma delay block 2h line memory sub- carrier recovery dto 12-bit adc 27mhz video timing and control block 27mhz xtal oscillator block pwrdn hsync field vsync href vref clock clock aff hff/qclk aef dv rd oe fifo control block and pixel output formatter llc synthesis with line- locked output clock i 2 c-compatible interface port sdata sclock reset alsb gl/clkin llc1 llc2 llcref elpf p19?0 pixel o/p port chroma comb filter digital output formats (20-bit wide bus): ycrcb (4:2:2 or 4:1:1) ccir601/ccir656 8-bit or extended 10-bit 0.5 v to 2.0 v p-p input range differential gain, 0.4% typ differential phase, 0.6 o typ programmable video controls: peak white/hue/brightness/saturation/contrast ccir/square/4 f sc pixel operation applications projectors digital tvs dvd-ram recorders and players pdp displays video decoders hybrid analog/digital set-top boxes professional equipment (continued on page 9)
rev. 0 ?2? ADV7185especifications 1 (v aa = 4.75 v to 5.25 v, v dd = 3.2 v to 3.5 v, v ddio = 3.15 v to 3.5 v, t min to t max 2 , unless otherwise noted.) parameter min typ max unit test conditions static performance resolution (each adc) 12 bits 12-bit range accuracy (each adc) integral nonlinearity 3 = = = = = = = =
rev. 0 ADV7185 ?3? video performance specifications 1, 2 parameter min typ max unit test conditions nonlinear specifications 2 differential phase 0.4 degree cvbs, comb/no comb differential gain 0.6 % cvbs, comb/no comb luma nonlinearity 0.5 % noise specifications 2 snr (ramp) 61 63 db cvbs analog front end channel crosstalk 63 db s-video/yuv, single-ended 63 db s-video/yuv, differential-ended lock time and jitter specifications 2 horizontal lock time 50 lines tv/vcr mode horizontal recovery time 50 lines horizontal lock range = = = = = = = = =
rev. 0 ?4? ADV7185 timing specifications 1 parameter min typ max unit test conditions system clock and crystal nominal frequency 27 mhz i 2 c port 3 scl clock frequency 0 400 khz scl min pulsewidth high, t 1 0.6 = = = = = = = ? = = = = = = =
rev. 0 ADV7185 ?5? sdata sclock t 3 t 2 t 6 t 1 t 7 t 5 t 4 t 3 t 8 figure 1. mpu port timing diagram llc1 llcref llc2 outputs p0ep19, href, vref, vsync, hsync, field, dv t 12 t 14 t 11 t 10 t 9 t 15 t 16 t 17 t 13 figure 2. llc clock, pixel port, and control outputs timing diagram clkin outputs p0ep19, href, vref, vsync, hsync, field, dv t 18 t 19 t 20 figure 3. pixel port and control outputs in capi and scapi mode timing diagram oe outputs p0ep19, hs, vs, vref, href, field, dv t 23 t 21 t 22 figure 4. oe
rev. 0 ?6? ADV7185 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADV7185 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 v aa to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v v ddio to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 v voltage on digital input pins . . gnd e 0.5 v to v aa + 0.5 v storage temperature (t s ) . . . . . . . . . . . . . . e65
rev. 0 ADV7185 ?7? pin function descriptions pin mnemonic input/output function 1 vs/vactive o vs or vertical sync. a dual-function pin, (om_sel[1:0] = 0, 0) is an output signal that indicates a vertical sync with respect to the yuv pixel data. the active period of this signal is six lines of video long. the polarity of the vs signal is controlled by the pvs bit. vactive (om_sel[1:0] = 1, 0 or 0, 1) is an output signal that is active during the active/viewable period of a video field. the polarity of vactive is controlled by the pvs bit. 2 hs/hactive o hs or horizontal sync. a dual-function pin, (om_sel[1:0] = 0, 0) is a pro- grammable horizontal sync output signal. the rising and falling edges can be controlled by hsb[9:0] and hse[9:0] in steps of 2 llc1. the polarity of the hs signal is controlled by the phs bit. hactive (om_sel[1:0] = 1, 0 or 0, 1) is an output signal that is active during the active/viewable period of a video line. the active portion of a video line is programmable on the ADV7185. the polarity of hactive is controlled by phs bit. 3, 14 dvssio g digital i/o ground 4, 15 dvddio p digital i/o supply voltage (3.3 v) 5e8, 17e24, p19ep0 o video pixel output port. 8-bit multiplexed ycrcb pixel port (p19ep12); 32e35, 73e76 16-bit ycrcb pixel port (p19ep12 = y and p9ep2 = cb,cr); 10-bit multi- plexed extended ycrcb pixel port (p19ep10); and 20-bit ycrcb pixel port (p19ep0). p0 represents the lsb. p1ep0 can also be configured as gpo [1] and gpo [0], and p11ep10 can be configured as gpo [3] and gpo [2] respectively. 9, 31, 71 dvss1edvss3 g ground for digital supply 10, 30, 72 dvdd1edvdd3 p digital supply voltage (3.3 v) 11 aff o almost full flag. a fifo control signal indicating when the fifo has reached the almost full margin set by the user (use ffm[4:0]). the polar- ity of this signal is controlled by the pff bit. 12 hff/qclk/gl i/o half full flag. a multifunction pin (om_sel[1:0] = 1, 0), it is a fifo control signal that indicates when the fifo is half full. the qclk (om_sel[1:0] = 0, 1) pin function is a qualified pixel output clock when using fifo scapi mode. the gl (om_sel[1:0] = 0, 0) function (genlock output) is a signal that contains a serial stream of data that contains information for locking the subcarrier frequency. the polarity of hff signal is controlled by the pff bit. 13 aef o almost empty flag. a fifo control signal, it indicates when the fifo has reached the almost empty margin set by the user (use ffm[4:0]). the polarity of this signal is controlled by the pff bit. 16 clkin i asynchronous fifo clock. this asynchronous clock is used to output data onto the p19-p0 bus and other control signals. 25 llcref o clock reference output. this is a clock qualifier distributed by the inter- nal cgc for a data rate of llc2. the polarity of llcref is controlled by the pllcref bit. 26 llc2 o line-locked clock system output clock/2 (13.5 mhz) 27 llc1/pclk o line-locked clock system output clock. a dual-function pin (27 mhz pwrdn pde ep p tep vdd svv
rev. 0 ?8? ADV7185 pin function descriptions (continued) pin mnemonic input/output function 39, 40, 47, 53, avss g ground for analog supply 56, 63 41, 43, 45, 57, avss1eavss6 g analog input channels. ground if single-ended mode is selected. these pins 59, 61 should be connected directly to refout when differential mode is selected. 42, 44, 46, 58, ain1eain6 i video analog input channels 60, 62 48, 49 capy1ecapy2 i adc capacitor network 50 avdd p analog supply voltage (5 v) 51 refout o internal voltage reference output 52 cml o common-mode level for adc 54, 55 capc1ecapc2 i adc capacitor network 64 reset sr so so t t s ttsp ps ps sdt o ppsdo so pps vre vreset o vrevros vreset vro spp n hreset hre hreset o hrehros ose vt hre hreset hro sppose spp n tphvr rd ores o dv o dvdvossppdv spp o ot o opdvo t pdv oe o eppo pp ed o oddevenos tp
rev. 0 ADV7185 ?9? (features continued from page 1) simplified digital interface on-board digital fifo optimized programmable video source modes: broadcast tv vcr/camcorder security/surveillance integrated on-chip video timing generator synchronous or asynchronous output timing line-locked clock output closed captioning passthrough operation vertical blanking interval support power-down mode 2-wire serial mpu interface (i 2 c-compatible) 5 v analog 3.3 v digital supply operation 80-lead lqfp package general description the ADV7185 is an integrated video decoder that automatically detects and converts a standard analog baseband television sig- nal compatible with worldwide standards ntsc or pal into 4:2:2 or 4:1:1 component video data compatible with 16-/8-bit ccir601/ccir656 or 10-/20-bit extended standards. the advanced and highly flexible digital output interface enables performance video decoding and conversion in both frame-buffer-based and line-locked, clock-based systems. this makes the device ideally suited for a broad range of applica- tions with diverse analog video characteristics, including tape-based sources, broadcast sources, security/surveillance cameras, and professional systems. fully integrated line stores enable real-time horizontal and vertical scaling of captured video down to icon size. the 12-bit accurate a/d conversion provides professional quality snr performance. this allows true 8-bit resolution in the 8-bit out- put mode, and broadcast quality in the 10-bit extended mode. the six analog input channels accept standard composite or advanced component video including s-video and ycrcb video signals in an extensive number of combinations. agc and clamp restore circuitry allow an input video signal peak- to-peak range of 0.5 v up to 2 v. alternatively, these can be bypassed for manual settings. the fixed 27 mhz clocking of the adcs and data path for all modes allows very precise and accurate sampling and digital filtering. the line-locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line-locked even with 2 sha 2 sha 2 mux y adc 2 c adc 2 notes analog signal path kept fully differential adcs: 12-bit a ccurate; 12db gain range 1 clamp blocks contain a set of current sources for dc restoration; u and v have only half bandwidth (sampled simultaneously, converted sequentially) 2 pipelined 12 12 clamp y 1 figure 5. analog front end block diagram clamping the clamp control on the ADV7185 consists of a digitally controlled analog current and voltage clamp and a digitally controlled digital clamp circuit. the coupling capacitor on each channel is used to store and filter the clamping voltage. a digital controller controls the clamp up and down current sources that charge the capacitor on every line. four current sources are used in the current clamp control, two large current sources are used for coarse clamping, and two small current sources are used for fine clamping. the voltage clamp, if enabled, is only used on startup or if a channel is switched; this clamp pulls the video into the midrange of the adc, which results in faster clamping and faster lock-in time for the decoder. the fourth clamp controller is fully digital and clamps the adc output data, which results in extremely accurate clamping. it also has the added advantage of being fully digital, which results in very fast clamp timing and makes the entire clamping process very robust in terms of handling large amounts of hum that can be present on real-world video signals. in s-video mode there are two clamp controllers used to sepa- rately control the luminance clamping and the chrominance
rev. 0 ?10? ADV7185 clamping. also, in ycrcb component input mode there are two clamp controllers used to control the luminance clamping and the crcb clamping separately; there are, however, individual current clamps on the cr and cb inputs. user programmability is built into the clamp controllers which enable the current and digital clamp controllers to be set up to user-defined conditions. refer to analog clamp control register (14h), digital clamp control register (15h), and digital color clamp offset register (15h and 16h) for control settings. analog-to-digital converters two 12-bit adcs are used in the ADV7185, and they run from a 27 mhz input clock. an integrated band gap generates the required reference voltages for the converters. if the decoder is configured in cvbs mode, the second adc can be switched off to reduce power consumption; see psc[1:0]. automatic gain control the agc control block on the ADV7185 is a digitally based system. this controller ensures that the input video signal (cvbs, s-video, or ycrcb) is scaled to its correct value such that the ycrcb digital output data matches the correct gain of the video signal. the agc has an analog input video range of 0.5 v p-p to 2.0 v p-p, which gives a e6 db to +6 db gain range. figure 6 demonstrates this range. this agc range will compensate for video signals that have been incorrectly termi- nated or have been attenuated due to cable loss, or other factors. there are two main control blocks: one for the luminance channel and one for the chrominance channel. the luminance automatic gain control has eight modes of operation: 1. manual agc mode where gain for luminance path is set manually using lgm[11:0]. 2. blank level to sync tip is used to set luminance gain; manual mire[2:0] controls the maximum value through luminance channel. there is no override of this mode when white peak mode is detected. 3. blank level to sync tip is used to set luminance gain; manual mire[2:0] controls the maximum value through luminance channel. there is override of this mode when white peak mode is detected. white peak mode is activated when the input video exceeds the maximum luminance range for long periods, this mode is designed to prevent clipping of the input video signal. 4. blank level to sync tip is used to set luminance gain; mire[2:0] is automatically controlled to set the maximum value through the luminance channel. there is no override of this mode when white peak mode is detected. 5. blank level to sync tip is used to set luminance gain; manual mire[2:0] is automatically controlled to set the maximum value through the luminance channel. there is override of this mode when white peak mode is detected. white peak mode is activated when the input video exceeds the maxi- mu m luminance range for long periods; this mode is designed to prevent clipping of the input video signal. 6. based on the active video peak white. pw_upd sets the gain update frequency (once per video per field). 7. based on the average active video. pw_res sets what lines are used, only relevant if the signal conforms to pal 625 line standard. 8. the luminance channel gain is frozen at its present value. 6 analog input level 2v p-p e db 0 e6 controlled adc input level e db 0 range = 12db maximum minimum figure 6. analog input range the chrominance automatic gain control has four modes of operation: 1. manual agc mode where gain for chrominance path is set manually using cgm[11:0]. 2. luminance gain used for chrominance channel. 3. chrominance automatic gain based on color burst amplitude. 4. chrominance gain frozen at its present setting. both the luminance and chrominance agc controllers have a programmable time constant that allows the agc to operate in four modes: slow, medium, fast, and video quality controlled. the maximum ire (mire[2:0]) control can be used to set the maximum input video range that can be decoded. table i shows the selectable range. table i. mire control function mire[2:0] pal (ire) ntsc (ire) 000 133 122 001 125 115 010 120 110 011 115 105 100 110 100 101 105 100 110 100 100 111 100 100
rev. 0 ADV7185 ?11? luminance processing figure 7 shows the luminance data path. the 12-bit data from the y adc is applied to an antialiasing low-pass filter that is designed to band-limit the input video signal such that aliasing does not occur. this filter dramatically reduces the design on an external analog antialiasing filter; this filter need only remove components in the input video signal above 22 mhz. the data then passes through a shaping or notch filter. when in cvbs mode, a notch filter must be used to remove the unwanted chrominance data that lies around the subcarrier frequency. a wide variety of programmable notch filters for both pal and ntsc are available. the ysfm[4:0] control the selection of these filters; refer to figures 8 and 9 for plots of these filters. if s-video or component mode is selected a notch filter is not required. the ADV7185 offers 18 possible shaping filters (svhs1-18) with a range of low-pass filter responses from 0.5 mhz up to 5.75 mhz. the ysfm[4:0] control the selection of these filters. please refer to figures 8 through 16 for filter plots. the next stage in the luminance processing path is a peaking filter. this filter offers a sharpness function on the luminance path. the degree of sharpness can be selected using ypm[2:0]. if no sharpness is required, this filter can be bypassed. the luminance data is then passed through a resampler to correct for line length variations in the input video. this resampler is designed to always output 720 pixels per line for standard pal or ntsc. the resampler used on the ADV7185 is of very high quality as it uses 128 phases to resample the video, giving 1/128 pixel resolution. the resampler is controlled by a sync detection block that calculates line length variations on the input video. the final stage in the luminance path, before it is applied to an output formatter block, is a 2-line delay store that is used to compensate for delays in the chroma datapath when chroma comb filter is selected. anti- aliasing lpf shaping and notch filter peaking filter resample delay line stores sync detection y adc data figure 7. luminance processing path frequency e mhz 0 e60 08 1 attenuat ion e db 23 45 67 e10 e20 e30 e40 e50 svhs1 svhs2 svhs3 svhs4 svhs5 svhs6 svhs7 svhs8 svhs9 svhs10 svhs11 svhs12 svhs13 svhs14 svhs15 svhs16 svhs17 svhs18 figure 8. luminance svhs1?svhs18 shaping filter responses frequency e mhz 1.0 e1.0 06 1 attenuat ion e db 2345 0.8 0.2 e0.4 e0.6 e0.8 0.6 0.4 0 e0.2 figure 9. luminance svhs1?svhs18 shaping filter responses (close-up) frequency e mhz 0 e60 08 1 at tenuation e db 23 45 67 e10 e20 e30 e40 e50 ntsc wn1 ntsc wn2 ntsc wn3 ntsc nn1 ntsc nn2 ntsc nn3 ntsc wn2 ntsc nn3 ntsc wn1 ntsc nn2 ntsc nn1 ntsc wn3 figure 10. luminance ntsc narrow/wide notch shaping filter
rev. 0 ?12? ADV7185 frequency e mhz 1.0 e1.0 0 4.0 0.5 attenuat ion e db 1.0 1.5 2.0 2.5 3.0 3.5 0.8 0.2 e0.2 e0.6 e0.8 0.6 0.4 0 e0.4 ntsc wn1 ntsc wn2 ntsc wn3 ntsc nn1 ntsc nn2 ntsc nn3 figure 11. luminance ntsc narrow/wide notch shaping filter (close-up) frequency e mhz 0 e60 08 1 attenuat ion e db 23 45 67 e10 e20 e30 e40 e50 p al nn1 p al nn2 p al nn3 p al w1 p al w2 p al nn3 p al w1 p al w2 p al nn2 p al nn1 figure 12. luminance pal narrow/wide notch shaping filter responses frequency e mhz 1.0 e1.0 0 4.0 0.5 attenuat ion e db 1.0 1.5 2.0 2.5 3.0 3.5 0.8 0.2 e0.2 e0.6 e0.8 0.6 0.4 0 e0.4 p al nn1 p al nn2 p al nn3 p al wn1 p al wn2 figure 13. luminance pal narrow/wide notch shaping filter responses (close-up) frequency e mhz 01234567 10 8 e8 attenuat ion e db 0 e2 e4 e6 4 2 6 ps1 ps4 ps3 ps2 ps5 ps6 figure 14. luminance peaking filter responses in s-video (svhs17 selected) frequency e mhz 0 7 123456 6 e10 attenuat ion e db 4 e2 e4 e6 e8 2 0 pc1 pc4 pc3 pc2 pc5 pc6 figure 15. luminance peaking filter responses in cvbs (pal nn3 selected) frequency e mhz 6 e8 0 6 1 attenuat ion e db 2345 4 2 0 e4 e6 e2 pc1 pc4 pc3 pc2 pc5 pc6 figure 16. luminance peaking filter responses in cvbs (ntsc nn3 selected)
rev. 0 ADV7185 ?13? chrominance processing figure 17 shows the chrominance data path. the 12-bit data from the y adc (cvbs mode) or the c adc (s-video) is first demodulated. the demodulation is achieved by multiplying by the locally generated quadrature subcarrier, where the sign of the cos subcarrier is inverted from line to line according to the pal switch, and then low-pass filtering is applied to removed components at twice the subcarrier frequency. for ntsc, the phase of the locally generated subcarrier during color burst is the same as the phase of the color burst. for pal, the phase of the color burst changes from line to line, relative to the phase during active video, and the phase of the locally generated subcarrier is the average of these two values. the chrominance data is then passed through an antialiasing filter, which is a band-pass filter to remove the unwanted lumi- nance data. this antialiasing filter dramatically reduces the external antialiasing filter requirements as it has only to filter components above 25 mhz. in component mode, the demodu- lation block is bypassed. the next stage of processing is a shaping filter that can be used to limit the chrominance bandwidth to between 0.5 mhz and 3 mhz; the csfm[2:0] can be used to select these responses. it should be noted that in cvbs mode, a filter of no greater than 1.5 mhz should be selected as cvbs video is typically band-limited to below 1.5 mhz. in s-video mode, a filter of up to 2 mhz can be used. in component mode, a filter of up to 3 mhz can be used as component video has higher bandwidth than cvbs or s-video. the chrominance data is then passed through a resampler to correct for line length variations in the input video. this resampler is designed to always output 720 pixels per line for standard pal or ntsc. the resampler used on the ADV7185 is of very high quality as it uses 64 phases to resample the video, giving 1/64 pixel resolution. the resampler is controlled by a sync detection block that calculates line length variations on the input video. the final stage in the chrominance path, before it is applied to an output formatter block, is chroma comb filter. anti- aliasing lpf shaping lpf resample chroma comb filters sync detection u/v cv/c 27mhz sine anti- aliasing lpf cosine 13.5mhz 13.5mhz 6.75mhz subcarrier recovery figure 17. chrominance processing path frequency e mhz 0 e60 0 4.0 0.5 attenuat ion e db 1.0 1.5 2.0 2.5 3.0 3.5 e10 e20 e30 e40 e50 sh2 sh3 sh4 sh5 sh6 sh1 figure 18. chrominance shaping filter responses frequency e mhz 1.0 e1.0 0 4.0 0.5 attenuat ion e db 1.0 1.5 2.0 2.5 3.0 3.5 0.8 0.2 e0.2 e0.6 e0.8 0.6 0.4 0 e0.4 sh2 sh3 sh4 sh5 sh1 sh6 figure 19. chrominance shaping filter responses (close-up)
rev. 0 ?14? ADV7185 output interface mode selection overview the ADV7185 supports three output interfaces: llc-compatible synchronous pixel interface, the capi interface, and scapi interface. when the part is configured in the synchronous pixel interface mode, pixel and control data are output synchronous with llc1 (8-bit or 10-bit mode) or llc2 (16-bit or 20-bit mode). in this mode, control and timing information for field, vertical blanking, and horizontal blanking identification may also be encoded as control codes. when configured in capi or scapi mode, only the active pixel data is output synchronous with the clkin (asynchronous fifo clock). the pixels are output via a 512-pixel deep 20-bit wide fifo. hactive and vactive are output on independent pins. hactive will be active during the active viewable period of a video line and vactive will be active during the active viewable period of a video field. capi and scapi modes will always output data in 16-bit or 20 -bit mode, so this mode of operation cannot be used when an 8-bit or 10-bit output interface is required. after power-up, the ADV7185 will default to the llc-compatible 8-bit ccir656 4:2:2 @ llc. synchronous pixel interface when the output is configured for an 8-bit pixel interface, the data is output on the pixel output port p[ 12 :19]; 10-bit pixel interface uses p[13:19]. in this mode, 10/8 b its of chrominance data will precede 8/10 bits of luminance data. new pixel data is output on the pixel port after each rising edge of llc1. when the output is configured for a 16-bit pixel interface, the lumi- nance data is output on p[19:12] and the chrominance data on p[2:9]. in this mode the data is output with respect to llc2. 20-bit pixel operation will use p[19:10] for luminance data and p[9:0] for chrominance data; as with the 16-bit mode data is output with respect to llc2 . figure 20 shows the b asic timing relationship for this mode. pixel data sav p[19e12][7:0] llc1 llc2 pixel data p[9e2][7:0] sav sav sav y0 y1 y2 y3 y4 cb0 cr0 cb1 cr1 cb2 00 ff xy 00 figure 20. synchronous pixel interface, 16-bit example
rev. 0 ADV7185 ?15? href dv vref vsync field sav/eav v bit sav/eav h bit sav/eav f bit cvbs input figure 21. ntsc end even field (llc mode) href dv vref vsync field sav/eav v bit sav/eav h bit sav/eav f bit cvbs input figure 22. ntsc end odd field (llc mode)
rev. 0 ?16? ADV7185 href dv vref vsync field sav/eav v bit sav/eav h bit sav/eav f bit cvbs input figure 23. pal end even field (llc mode) href dv vref vsync field sav/eav v bit sav/eav h bit sav/eav f bit cvbs input figure 24. pal end odd field (llc mode)
rev. 0 ADV7185 ?17? control and pixel interface fifo modes when the ADV7185 is configured to operate in this mode, pixel data generated within the part is buffered by a 512-pixel deep fifo. only active video pixels and control codes are written into the fifo; the others have been dropped. in this mode, the output is operating asynchronously and a clkin must be provided to clock pixels out of the fifo. the clkin must operate faster than the effective data transfer rate into the fifo. this rate will be determined by the number of active pixels per line. if the clkin is not above this, the fifo may overflow. the ADV7185 controls the fifo when set to operate in scapi mode. dv (data valid) is internally fed back to the rd (read enable), unlike the synchronous pixel mode where dv will not ind icate the validity of the current pixel and only acts as an indication of how much data is stored in the fifo. dv will go high at the same time as aff and remain high until the fifo is empty. by internally setting dv to rd , the system ensures that the fifo never overflows. when using this mode, the status of data on the pixel outputs can be determined by two indicators, dv and qclk. dv will go active two clock cycles (llc1) before valid data appears on the bus. qclk is a qualified clock derived from clkin, but will only be present when valid pixel data is output from the fifo. dv indicates valid pixel or control code data. using these two control signals, the user can differentia te between pixel information and invalid data. figure 25 shows the basic timing relationship for this mode. the operation of the ADV7185 in capi mode is similar to that of scapi mode with the exception that now the fifo is con- trolled by the system; the system must monitor the almost full flag (aff), the almost empty flag (aef), and control the fifo read enable (rd). unlike scapi mode, the qclk is not gated and is therefore continuous. figure 26 shows the basic timing relationship of this mode. pixel data dv clkin qclk aff aef notes 1. the polarity of aff and aef are controlled by the pff bit. 2. dv polarity is set by the pdv bit. figure 25. scapi output mode fifo operation rd clkin qclk aff aef th e polarity of aff and aef are controlled by the pff bit. data figure 26. capi output mode fifo operation
rev. 0 ?18? ADV7185 manual clock control the ADV7185 offers several output clock mode options: the output clock frequency can be set by the input video line length, a fixed 27 mhz output, or by a user-programmable value. informa- tion on the clock control register at 28h can be found in the register access map. when bit 6 of this register (clkmane) is set to logic 1, the output clock frequency will be determined by the user-programmable value (clkval[15:0]). using this mode, the output clock frequency is calculated as: llc clkval mhz = for example, a required clock frequency of 25 mhz would yield a clkval of 2d266h (184934). color subcarrier control the color subcarrier manual frequency control register ( csmf[27:0]) can be used to set the ddfs block to a user- defined frequency. this function can be useful if the color subcarrier frequency of the incoming video signal is outside the standard f sc lock range. setting bit 4 reg 23h (csm) to a logic 1 enables the manual frequency control, the frequency of which will be determined by csmf[27:0]. the value of csmf[27:0] can be calculated as: csmf f mhz sc [:] 27 0 2 27 28 = * required mpu port description the ADV7185 supports a 2-wire serial (i 2 c-compatible) micro- processor bus driving multiple peripherals. two inputs, serial data (sdata) and serial clock (sclock), carry information between any device connected to the bus. each slave device is recognized by a unique address. the ADV7185 has two possible slave addresses for both read and write operations. these are unique addresses for the device and are illustrated in figure 27. the lsb sets either a read or write operation. logic level 1 corresponds to a read operation while logic level 0 corre- sponds to a write operation. a1 is set by setting the alsb pin of the ADV7185 to logic level 0 or logic level 1. 1 0 0 0 1 0 a1 x address control set up by alsb read/write control 0 write 1 read figure 27. slave address to control the device on the bus the following protocol must be followed. first the master initiates a data transfer by estab- lishing a start condition, defined by a high to low transition on sdata while sclock remains high. this indicates that an address/data stream will follow. all peripherals respond to the st art condition and shift the next 8 bits (7-bit address + r/ w t sst t t sdt so tr w s s tdvt sdt r w tdv t t s dso dv t sdt dv
rev. 0 ADV7185 ?19? write sequence read sequence s slave addr a(s) data sa (s) slave addr sub addr sub addr a(s) a(s) s a(s) slave addr a(s) data a(m) data a(s) p data a (m) p lsb = 0 lsb = 1 s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a (s) = no-acknowledge by slave a (m) = no-acknowledge by master figure 28. write and read sequences sdata sclock 1e7 8 9 1e7 8 9 1e7 8 9 start addr r/ w ac ks ub addr ack data ack stop s p figure 29. bus data transfer
rev. 0 ?20? ADV7185 register accesses the mpu can write to or read from all of the registers of the ADV7185 except the subaddress register, which is a write only register. the subaddress register determines which register the next read or write operation accesses. all communications with the part through the bus start with an access to the subaddress register. then a read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. register programming the following section describes each register in terms of its configuration. subaddress register (sr7esr0) the communications register is an 8-bit write only register. after the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. the subaddress register deter- mines to/from which register the operation takes place. table ii shows the various operations under the control of the s ubaddress register. zero should always be written to sr7esr6. register select (sr5esr0) these bits are set up to point to the required starting address. table ii. subaddress register register name addr (hex) basic block input control 00 video selection 01 video enhancement control 02 output control 03 extended output control 04 general-purpose output 05 reserved 06 fifo control 07 contrast control 08 saturation control 09 brightness control 0a hue control 0b default value y 0c default value c 0d temporal decimation 0e power management 0f status register 10 info register 11 register name addr (hex) advanced block reserved 12 analog control (internal) 13 analog clamp control 14 digital clamp control 1 15 digital clamp control 2 16 shaping filter control 17 reserved 18 comb filter control 19 reserved 1a reserved 1b reserved 1c reserved 1d reserved 1e reserved 1f reserved 20 reserved 21 reserved 22 color subcarrier control 1 23 color subcarrier control 2 24 color subcarrier control 3 25 color subcarrier control 4 26 pixel delay control 27 manual clock control 1 28 manual clock control 2 29 manual clock control 3 2a auto clock control 2b agc mode control 2c chroma gain control 1 2d chroma gain control 2 2e luma gain control 1 2f luma gain control 2 30 manual gain shadow control 1 31 manual gain shadow control 2 32 misc gain control 33 hsync position control 1 34 hsync position control 2 35 hsync position control 3 36 polarity control 37 reserved 44 reserved 45 reserved f1 reserved f2
rev. 0 ADV7185 ?21? table iii. basic registers addr register (hex) d7 d6 d5 d4 d3 d2 d1 d0 input control 00 vid sel.3 vid sel.2 vid sel.1 vid sel.0 insel.3 insel.2 insel.1 insel.0 video selection 01 ase betacam 4fsc diffin sqpe vid vid qual.1 qual.0 video enhancement 02 cor.1 cor.0 ypm.2 ypm.1 ypm.0 control output control 03 vbi en tod of sel.3 of sel.2 of sel.1 of sel.o om sel.1 omel.o extended output 04 bt656-4 range control general-purpose 05 hl_en bl_c_vbi gpeh gpel gp0.3 gp0.2 gp0.1 gp0.0 output reserved 06 fifo control 07 ffst afr fr ffm.4 ffm.3 ffm.2 ffm.1 ffm.0 contrast control 08 con.7 con.6 con.5 con.4 con.3 con.2 con.1 con.0 saturation control 09 sat.7 sat.6 sat.5 sat.4 sat.3 sat.2 sat.1 sat.0 brightness control 0a bri.7 bri.6 bri.5 bri.4 bri.3 bri.2 bri.1 bri.0 hue control 0b hue.7 hue.6 hue.5 hue.4 hue.3 hue.2 hue.1 hue.0 default value y 0c def y.5 def y.4 def y.3 def y.2 def y.1 def y.0 def_ def_ auto_en val_en default value c 0d def c.7 def c.6 def c.5 def c.4 def c.3 def c.2 def c.1 def c.0 temporal 0e tdr.3 tdr.2 tdr.1 tdr.0 tdc.1 tdc.0 tde decimation power management 0f res traq pwrdn ps cg ps ref pdbp psc.1 psc.0 status register 10 status.7 status.6 status.5 status.4 status.3 status.2 status.1 status.0 info register 11 ident.7 ident.6 ident.5 ident.4 ident.3 ident.2 ident.1 ident.0 table iv. advanced registers addr register (hex) d7 d6 d5 d4 d3 d2 d1 d0 reserved 12 reserved 13 tim_oe analog clamp 14 vclen cclen facl.1 facl.0 ficl.1 ficl.0 control digital clamp 15 dccm dct.1 dct.0 dcfe dcc0.11 dcc0.10 dcc0.9 dcc0.8 control 1 digital clamp 16 dcc0.7 dcc0.6 dcc0.5 dcc0.4 dcc0.3 dcc0.2 dcc0.1 dcc0.0 control 2 shaping filter 17 csfm.2 csfm.1 csfm.0 ysfm.4 ysfm.3 ysfm.2 ysfm.1 ysfm.0 control reserved 18 comb filter control 19 ccmb_ad ccm.1 ccm.0 color subcarrier 23 csm csmf.27 csmf.26 csmf.25 csmf.24 control 1
rev. 0 ?22? ADV7185 table iv. advanced registers (continued) addr register (hex) d7 d6 d5 d4 d3 d2 d1 d0 color subcarrier 24 csmf.23 csmf.22 csmf.21 csmf.20 csmf.19 csmf.18 csmf.17 csmf.16 control 2 color subcarrier 25 csmf.15 csmf.14 csmf.13 csmf.12 csmf.11 csmf.10 csmf.9 csmf.8 control 3 color subcarrier 26 csmf.7 csmf.6 csmf.5 csmf.4 csmf.3 csmf.2 csmf.1 csmf.0 control 4 pixel delay control 27 swpc cta.2 cta.1 cta.0 manual clock 28 fix27e clkmane clkval. clkval. control 1 17 16 manual clock 29 clkval. clkval. clkval. clkval. clkval. clkval. clkval.9 clkval.8 control 2 15 14 13 12 11 10 manual clock 2a clkval.7 clkval.6 clkval.5 clkval.4 clkval.3 clkval.2 clkval.1 clkval.0 control 3 auto clock control 2b acklm.2 acklm.1 acklm.0 agc mode control 2c lagc.2 lagc.1 lagc.0 cagc.1 cagc.0 chroma gain 2d cagt.1 cagt.0 cmg.11 cmg.10 cmg.9 cmg.8 control 1 chroma gain 2e cmg.7 cmg.6 cmg.5 cmg.4 cmg.3 cmg.2 cmg.1 cmg.0 control 2 luma gain 2f lagt.1 lagt.0 lmg.11 lmg.10 lmg.9 lmg.8 control 1 luma gain 30 lmg.7 lmg.6 lmg.5 lmg.4 lmg.3 lmg.2 lmg.1 lmg.0 control 2 manual gain 31 sgue lmgs.11 lmgs.10 lmgs.9 lmgs.8 shadow control 1 manual gain 32 lmgs.7 lmgs.6 lmgs.5 lmgs.4 lmgs.3 lmgs.2 lmgs.1 lmgs.10 shadow control 2 misc gain control 33 cke mire.2 mire.1 mire.0 av_al pw_upd hsync position 34 hsb.9 hsb.8 hse.9 hse.8 control 1 hsync position 35 hsb.7 hsb.6 hsb.5 hsb.4 hsb.3 hsb.2 hsb.1 hsb.0 control 2 hsync position 36 hse.7 hse.6 hse.5 hse.4 hse.3 hse.2 hse.1 hse.0 control 3 polarity control 37 phs phvr pvs pllcr pf pdv pff pclk resample control 44 fsc_inv reserved 45 reserved f1 reserved f2
rev. 0 ADV7185 ?23? table v. input control register (subaddress 00) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting insel[3:0] 1 0000 cvbs in on ain1 2 0001 cvbs in on ain2 0010 cvbs in on ain3 0011 cvbs in on ain4 0100 cvbs in on ain5 0101 cvbs in on ain6 0110 y on ain1 , c on ain4 3 0111y on ain2, c on ain5 1000y on ain3, c on ain6 1001 y on ain1 , u on ain4 , v on ain5 4 1010y on ain2, u on ain3, v on ain6 vid_sel[3:0] 5 0000 a uto detect pal (bghid), ntsc without pedestal 0001 auto detect pal (bghid), ntsc (m) with pedestal 0010 auto detect pal (n), ntsc (m) without pedestal 0011 auto detect pal (n), ntsc (m) with pedestal 0100 ntsc (m) without pedestal 0101 ntsc (m) with pedestal 0110 ntsc 4.43 without pedestal 0111 ntsc 4.43 with pedestal 1000 pal bghid without pedestal 1001 pal n with pedestal 1010 pal m without pedestal 1011 pal m with pedestal 1100 pal combination n 1101 pal combination n with pedestal notes 1 allows the user to select an input channel as well as the input format. 2 composite 3 s-video 4 yuv 5 allows the user to select the input video standard. table vi. video selection register (subaddress 01) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting vid_qual[1:0] 1 00broa dcast quality 01 tv quality 10vcr qu ality 11 surveillance quality sqpe 2 0s tandard mode 1 enable square pixel mode diffin 3 0s ingle-ended inputs 1d ifferential inputs ffsc 4 0s tandard video operation 1 select 4 f sc mode 5 betacam 0 standard video input 1b etacam input enable reserved 0 set to zero ase 6 1i nsel change will not cause reacquire. 0i nsel change will trigger reacquire. notes 1 allows the user to influence the time constant of the system depending on the input video quality. 2 allows the user to enable/disable the square pixel operation. 3 allows the user to select a differential input mode for every entry in the insel[3:0] table. 4 4 f sc mode. allows the selection of a special ntsc mode where the data is resampled to 4 f sc sampling rate. as a result the llc will operate at a 4 f sc rate as well. only valid for ntsc input. 5 ntsc only 6 automatic startup enable. when set a change in the insel register will automatically be detected and lead the device to enter a video reacquire mode. may be disabled for genlocked video sources.
rev. 0 ?24? ADV7185 table vii. video enhancement control register (subaddress 02) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting ypm[2:0] 1 000 c = 4.5 db, s = 9.25 db 2 001 c = 4.5 db , s = 9.25 db 3 010c = 4.5 db, s = 5.75 db 011c = 1.25 db, s = 3.3 db 100 no change; c = 0, s = 0 101c = e1.25 db, s = e3 db 110c = e1.75 db, s = e8 db 111c = e3.0 db, s = e8 db cor[1:0] 4 00 no coring 01 truncate if y < black + 8 10 tr uncate if y < black + 16 11 tr uncate if y < black + 32 reserved 0 0 0 set to zero notes 1 y peaking filter mode. allows the user to boost/attenuate luma signals around the color subcarrier frequency. used to enhance t he picture and improve the contrast. 2 c = composite (2.6 mhz) 3 s = s-video (3.75 mhz) 4 coring selection. controls optional coring of the y output signal depending on its level. table viii. output control register (subaddress 03) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting om_sel[1:0] 1 00 philips-compatible 01 broktree api a-compatible 10 broktree api b-compatible 11not va lid setting of_sel[3:0] 2 0000 10-bit @ llc 4:2:2 ccir656 0001 20-bit @ llc2 4:2:2 ccir656 0010 16-bit @ llc2 4:2:2 ccir656 0011 8-bit @ llc 4:2:2 ccir656 0100 12-bit @ llc2 4:1:1 0101 not used 0110 not used 0111 not used 1000 not used 1001 not used 1010 not used 1011 not used 1100 not used 1101 not used 1110 not used 1111 not used tod 3 0 drivers dependent on oe p dtsr oe p ven s vro notes oss tsod oe v
rev. 0 ADV7185 ?25? table ix. extended output control register (subaddress 04) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting range 1 0 ccir-compliant 1f ill whole accessible range reserved 1 1 0 ddos[2:0] 2 000 no additional data 3 bt656-4 4 0b t656-3-compatible 1 bt656-4-compatible notes 1 allows the user to select the range of output values. can be ccir601-compliant or fill the whole accessible number range. 2 d data output selection. if the 100-pin package is used, the 12 additional pins can output additional data. 3 12 pins three-state 4 allows the user to select an output mode that is compatible with bt656-4 or bt656-3. table x. general-purpose output register (subaddress 05) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting gpo[3:0] 1 0000user programmable pixel data valid off gpel 2 0g po[1:0] three-stated 1g po[1:0] enabled gpeh 3 0g po[3:2] three-stated 1g po[3:2] enabled bl_c_vbi 4 0d ecode and output color during vbi 1blank cr and cb data during vbi hl_en 5, 6 0g po[0] pin function 1gpo[0 ] shows hlock status notes 1 pixel data valid off. these general-purpose output pins may be programmed by the user but are only available in selected output modes of_sel[3:0] and when the output drivers are enabled using gpel, gpeh, and hl_enable bits. 2 general-purpose enable low. enables the output drivers for the general-purpose outputs bits 0 and 1. 3 general-purpose enable high. enables the output drivers for the general-purpose outputs bits 2 and 3. 4 blank chroma during vbi. 5 hlock enable. this bit causes the gpo[0] pin to output hlock instead of gpo[0]. only available in certain output modes. 6 gpo lower bits must be enabled gpel. disabled. table xi. fifo control register (subaddress 07) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting ffm[4:0] 1 00100user-programmable fr 2 0norma l operation 1 fifo reset 3 afr 4 0no auto reset 1aut o reset ffst 5 0s ynchronous to clkin 1s ynchronous to 27 mhz notes 1 fifo flag margin. allows the user to program the location at which the fifo flags aef and aff. 2 fifo reset. setting this bit will cause the fifo to reset. 3 bit is auto-cleared. 4 automatic fifo reset. setting this bit will cause the fifo to automatically reset at the end of each field of video. 5 fifo flag self time. sets whether the fifo flags aef, aff, and hff are output synchronous to the external clkin of the 27 mhz i nternal clock. table xii. contrast register (subaddress 08) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting con[7:0] * 10000000 * contrast adjust. this is the user control for contrast adjustment.
rev. 0 ?26? ADV7185 table xiii. saturation register (subaddress 09) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting sat[7:0] * 00000000 e42 db 100000000 db 111111116 db * saturation adjust. allows the user to adjust the saturation of color output. table xiv. brightness register (subaddress 0a) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting bri[7:0] * 000000000 db 011111113 db 10000000e3 db * controls the brightness of the video signal. range = = = =
rev. 0 ADV7185 ?27? table xviii. temporal decimation register (subaddress 0e) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting tde 1 0 disabled 1 enabled tdc[1:0] 2 00 suppress frames; start with even field 01 suppress frames; start with odd field 10 suppress even fields only 11 suppress odd fields only tdr[3:0] 3 0000 skip none 0001 skip 1 field/frame 0010 skip 2 fields/frames 0011 skip 3 fields/frames 0100 skip 4 fields/frames 0101 skip 5 fields/frames 0110 skip 6 fields/frames 0111 skip 7 fields/frames 1000 skip 8 fields/frames 1001 skip 9 fields/frames 1010 skip 10 fields/frames 1011 skip 11 fields/frames 1100 skip 12 fields/frames 1101 skip 13 fields/frames 1110 skip 14 fields/frames 1111 skip 15 fields/frames reserved 0 set to zero notes 1 temporal decimation enable. allows the user to enable/disable the temporal function. configured using tdc[1:0] and tdr[3:0]. 2 temporal decimation control. allows the user to select the suppression of selected fields of video. 3 temporal decimation rate. specifies how many fields/frames to be skipped before a valid one is output. as specified in the tdc[ 1:0] register. table xix. power management register (subaddress 0f) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting psc[1:0] 1 00 full operation 01 cvbs input only 10 digital only 11 power save mode pdbp 2 0 power-down controller by pin 1 power-down controller by bit ps_ref 3 0r eference functional 1 reference in power save mode ps_cg 4 0c lock generator functional 1 cg in power save mode pwrdn 5 0 system functional 1 power-down traq 6 0 normal operation 1r equire video signal reset 7 0 1 resets di g ital core and i 2 c notes 1 power save control. allows a set of different power save modes to be selected. 2 power-down bit priority. there are two ways to shut down the digital core; the power-down bit sets which has higher priority. 3 power save reference. allows the user to enable/disable the internal analog reference. 4 power save for the llc clock generator 5 power-down. disables the input pads and powers down the 27 mhz clock. 6 timing reacquire. will cause the part to reacquire the video signal and is the software version of the iso pin. if bit is set w ill clear itself on the next 27 mhz clock cycle. 7 resets digital core and i 2 c; self-clearing bit.
rev. 0 ?28? ADV7185 table xx. status register 1 (subaddress 10) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting status[7:0] 2 0 1 color kill active 0 1 white peak active 0 1 adc overflow detected 0 1 adc underflow detected 0 1 50 hz field rate auto detected 0 1 f sc locked (current) 0 1 lost lock (since last read) 0 1 in lock (current) notes 1 read only 2 provides information about the internal status of the decoder. table xxi. info register 1 (subaddress 11) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting ident[7:0] 2 xxxxxxxx0 = v85a, 3 = v85b, 4 = v85b3 notes 1 read only 2 provides identification on the revision of the part. table xxii. analog control internal register (subaddress 13) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting tim_oe * 0 dependent on oe o eee o e oe tod t rs d rs o o o o o o o o en sso se ven vd ve reserved s notes e ve
rev. 0 ADV7185 ?29? table xxiv. digital clamp control 1 register (subaddress 15) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting dcco[11:8] 1 xxxx only applicable if dccm is set to manual offset mode. dcfe 2 0 digital clamp operational 1 digital clamp frozen dct[1:0] 3 00 slow (tc = 1 second) 01 medium (tc = 0.5 second) 10 fast (tc = 0.1 second) 11 dependent on vid_qual dccm[7:0] 4 0a utomatic digital clamp 1m anual offset correction notes 1 (digital color clamp offset) holds upper 4 bits of the digital offset value which is added to the raw data from the adc before entering the core. 2 (digital clamp freeze enable) allows the user to freeze the digital clamp loop at any point in time. 3 (digital clamp timing) determines the time constant of the digital clamping circuitry. 4 (digital color clamp mode) sets the mode of operation for the digital clamp circuitry. offset correction via dcco for c only. table xxv. digital clamp control 2 register (subaddress 16) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting dcco[7:0] * xxxxxxxx * digital color clamp offset. holds the lower 8 bits of the digital offset value which is added to the raw data from the adc befo re entering the core. only applicable if dccm is set to manual offset mode. table xxvi. shaping filter control register (subaddress 17) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting ysfm[4:0] 1 00000 auto wide notch 00001 auto narrow notch 00010 svhs 1 eeeeee 10010 svhs 17 10011 pal nn1 10100 pal nn2 10101 pal nn3 10110 pal wn 1 10111 pal wn 2 11000ntsc nn1 11001ntsc nn2 11010ntsc nn3 11011 ntsc wn1 11100 ntsc wn2 11101 ntsc wn3 11110 not used 11111 svhs 18 csfm[2:0] 2 000 auto selection 1.5 mhz 001 auto selection 2.17 mhz 010 sh1 eee e 110 sh5 111 sh6 notes 1 y shaping filter mode. allows the user to select a wide range of low-pass and notch filters. 2 c shaping filter mode. allows the selection from a range of low-pass chrominance filters. auto = filter selected based on scali ng factor.
rev. 0 ?30? ADV7185 table xxvii. comb filter control register (subaddress 19) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting reserved 0 0 0 0 0 set to zero ccm[1:0] 1 00 no comb 01 1h 10 2h 11 not va lid, do not use ccmb_ad 2 0 chroma comb nonadaptive 1 chroma comb adaptive notes 1 chroma comb mode. selects a primary mode for the filter. 2 chroma comb adaptive table xxviii. color subcarrier control 1 register (subaddress 23) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting csmf[27:24] 1 xxxx csm 2 0ma nual fsc disabled 1 user-defined fsc 3 reserved 1 1 1 set to one notes 1 color subcarrier manual frequency. holds the value used to enable the user to support odd subcarrier frequencies. 2 color subcarrier manual 3 defined in csfm[27:0] table xxix. color subcarrier control 2 register (subaddress 24) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting csmf[23:16] * xxxxxxxx * color subcarrier manual frequency. holds the value used to enable the user to support odd subcarrier frequencies. table xxx. color subcarrier control 3 register (subaddress 25) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting csmf[15:8] * xxxxxxxx * color subcarrier manual frequency. holds the value used to enable the user to support odd subcarrier frequencies. table xxxi. color subcarrier control 4 register (subaddress 26) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting csmf[7:0] * xxxxxxxx * color subcarrier manual frequency. holds the value used to enable the user to support odd subcarrier frequencies.
rev. 0 ADV7185 ?31? table xxxii. pixel delay control register (subaddress 27) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reserved 000 set to zero cta[2:0] 1 000 not valid 001 chroma + 2 pixel (early) 010 chroma + 1 pixel (early) 011 no delay 100 chroma e 1 pixel (late) 101 chroma e 2 pixel (late) 110 chroma e 3 pixel (late) 111 not valid reserved 1 set to one swpc 2 0 no swapping 1 swap the cr and cb values notes 1 chroma timing adjust. allows a specified timing difference between the luma and chroma samples. 2 allows the cr and cb samples to be swapped. table xxxiii. manual clock control 1 register (subaddress 28) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting clkval[17:16] 1 xx reserved 1111 set to d efault clkmane 2 0 output frequency set by video 1 frequency set by clkval[17:0] fix27e 3 0 output frequency set by clock generator 1 output 27 mhz fixed notes 1 if enabled via clkmane, clkval[17:0] determines the fixed output frequency. on the llc, llc2, and llcref pins. 2 clock generator manual enable. allows the analog clock generator to produce a fixed clock frequency that is not dependent on th e video signal. 3 allows the o/p of fixed 27 mhz crystal clock via llc, llc2, and llcr ef o/p pins. table xxxiv. manual clock control 2 register (subaddress 29) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting clkval[15:8] * xxxxxxxx * if enabled via clkmane, clkval[17:0] determines the fixed output frequency. on the llc, llc2, and llcref pins. table xxxv. manual clock control 3 register (subaddress 2a) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting clkval[7:0] * xxxxxxxx * if enabled via clkmane, clkval[17:0] determines the fixed output frequency. on the llc, llc2, and llcref pins.
rev. 0 ?32? ADV7185 table xxxvi. auto clock control register (subaddress 2b) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting reserved 00000 set to zero aclkn[2:0] * 000 color burst line 001 start line 24 color burst line 010 active video 011 active video (<304) pal, (<264) ntsc 100 active video (<304) pal, (<256) ntsc 101 active video (<319/320) pal, (<273/274) ntsc 110 invalid 111 invalid * automatic clock generator mode. influences the mode of operation for the llc. only when not in manual mode. table xxxvii. agc mode control register (subaddress 2c) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting cagc[1:0] 1 00 manual fixed gain. use cmg [11:0] 01us e luma gain for chroma 10automa tic gain. based on color burst 11fr eeze chroma gain reserved 1 1 set to one lagc[2:0] 2 000 manual fixed gain 3 001 agc no override through white peak; man ire control 4 010 agc auto override through white peak; man ire control 4 011 agc no override through white peak; man ire control 4 100 agc auto override through white peak; man ire control 4 101 a gc active video with white peak 110 a gc active video with average video 111 freez e gain reserved 1 set to one notes 1 chroma automatic gain control. selects the basic mode of operation for the agc in the chroma path. 2 luma automatic gain control. selects the mode of operation for the gain control in the luma path. 3 use lmg[11:0]. 4 blank level to sync tip. table xxxviii. chroma gain control 1 register (subaddress 2d) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting cmg[11:8] 1 xxxx reserved 1 1 set to one cagt[1:0] 2 00 slow ( tc = 2 sec) 01 medium (tc = 1 sec) 10 fa st (tc = 0.2 sec) 11 dependent on vid_qual notes 1 chroma manual gain. can be used to program a desired manual chroma gain or read back the actual used gain value. cagc[1:0] sett ings will decide in which mode cmg[11:0] will operate. 2 chroma automatic gain timing. allows adjustment of the chroma agc tracking speed. will only have effect if cagc[1:0] is set to auto gain (10b). table xxxix. chroma gain control 2 register (subaddress 2e) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting cmg[7:0] * xxxxxxxx * chroma manual gain. lower 8 bits, see cmg [11:8] for description.
rev. 0 ADV7185 ?33? table xl. luma gain control 1 register (subaddress 2f) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting lmg[11:8] 1 xxxx reserved 1 1 set to one lagt[1:0] 2 00 slow ( tc = 2 sec) 01 medium (tc = 1 sec) 10 fa st (tc = 0.2 sec) 11 dependent on vid_qual notes 1 luma manual gain. can be used to program a desired manual chroma gain or read back the actual used gain value. lagc[1:0] settin gs will decide in which mode lmg[11:0] will operate. 2 luma automatic gain timing. allows adjustment of the luma agc tracking speed. will only have effect if lagc[1:0] is set to auto gain (10b). table xli. luma gain control 2 register (subaddress 30) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting lmg[7:0] * xxxxxxxx * luma manual gain. can be used program a desired manual chroma gain or read back the actual used gain value. table xlii. manual gain shadow control 1 register (subaddress 31) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting lmgs[11:8] 1 xxxx reserved 1 1 1 set to one sgue 2 0d isable lmgs update 1 use lmgs update facility notes 1 luma manual gain store. has dual functions; a desired manual luma gain can be programmed or a readback from the register will r eturn the actual gain used. gain value will only become active when lagc[2:0] set to manual fixed gain. the function and readback value are dependent on lagc[2: 0] setting. 2 surveillance gain update enable. enables surveillance mode operation (see lmgs[11:0] for details). table xliii. manual gain shadow control 2 register (subaddress 32) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting lmg[7:0] * xxxxxxxx * chroma manual gain. lower 8 bits, see lmg[11:8] for description. table xliv. miscellaneous gain control register (subaddress 33) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting pw_upd 1 0 update gain once per line 1 update gain once per field av _ a l 2 0li nes 33 to 310 1li nes 33 to 270 mire[2:0] 3 000 pa l-133 ntsc-122 001 pa l-125 ntsc-115 010 pa l-120 ntsc-110 011 pa l-115 ntsc-105 100 pa l-110 ntsc-100 101 pa l-105 ntsc-100 110 pa l-100 ntsc-100 111 pa l-100 ntsc-100 reserved 1 set to one cke 4 0 color kill disabled 1 color kill enabled reserved 1 set to one notes 1 peak white update. determines the gain based on measurements taken from the active video; this bit determines the rate of gain change. lagc[1:0] must be set to the appropriate mode to enable peak white or average video in the first case. 2 average brightness active lines. allows the selection between two ranges of active video to determine the average brightness. 3 max ire. sets the max i/p ire level depending on the video standard. 4 color kill enable. allows the optional color kill function to be switched on or off.
rev. 0 ?34? ADV7185 table xlv. hsync position control 1 register (subaddress 34) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting reserved 1111 set to one hse[9:8] 1 00 hsync ends after hse[9:0] pixel after falling edge of hs y nc. hsb[9:8] 2 00 hsync starts after hsb[9:0] pixel after the falling ed g e of hs y nc. notes 1 hsync end. allows the positioning of the hsync output within the video line. 2 hsync begin. allows the positioning of hsync output within the video line. table xlvi. hsync position control 2 register (subaddress 35) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting hsb[7:0] 00000001 1 1 using hsb[9:0] and hse[9:0] the user can program the position and length of hsync output signal. table xlvii. hsync position control 3 register (subaddress 36) bit description bit 7 bit 6 bit 5 bit 4 b it 3 bit 2 bit 1 bit 0 register setting hse[7:0] 00000000 1 1 using hsb[9:0] and hse[9:0] the user can program the position and length of hsync output signal.
rev. 0 ADV7185 ?35? table xlviii. polarity register (subaddress 37) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting pclk 1 0 active high 1 active low pff 2 0 active high 1 active low pdv 3 0 active high 1 active low pf 4 0 active high 1 active low pllcr 5 0 active high 1 active low pvs 6 0 active high 1 active low phvr 7 0 active high 1 active low phs 8 0 active high 1 active low notes 1 sets the polarity of llc, llc2, and qclk. 2 sets the polarity of hff, aef, and aff. 3 sets the polarity for data field. 4 sets the field sync polarity. 5 sets the llcref polarity. 6 sets the vsync polarity. 7 sets the href and vref sync polarities. 8 sets hsync polarity.
rev. 0 ?36? ADV7185 table xlix. resample control register (subaddress 44) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r egister setting reserved 000001set to d efault fsc_inv * x nb no default value 0 compatible with adv7190, adv7191, and adv7194 1 compatible with adv717x reserved 0 set to zero * color subcarrier rtco inversion. allows the inversion of the gl bit. table l. reserved (subaddress 45) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting 001 xx 011 default values 10111011set to these values reserved functions table li. reserved (subaddress f1) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting 1111011x default values 11101111set to these values reserved functions table lii. reserved (subaddress f2) bit description bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register setting 1001110x default values 10000000set to these values reserved functions
rev. 0 ADV7185 ?37? addr default register (hex) (hex) basic block input control 00 00 video selection 01 80 video enhancement control 02 04 output control 03 0c extended output control 04 0c general-purpose output 05 40 reserved 06 xx fifo control 07 04 contrast control 08 80 saturation control 09 80 brightness control 0a 0 hue control 0b 0 default value y 0c 10 default value c 0d 88 temporal decimation 0e 00 power management 0f 00 status register 10 info register 11 table liii. power-on reset values for mpu registers addr default register (hex) (hex) advanced block reserved 12 xx analog control (internal) 13 45 analog clamp control 14 18 digital clamp control 1 15 6x digital clamp control 2 16 xx shaping filter control 17 01 reserved 18 xx comb filter control 19 10 reserved 1a xx reserved 1b xx reserved 1c xx reserved 1d xx reserved 1e xx reserved 1f xx reserved 20 xx reserved 21 xx reserved 22 xx color subcarrier control 1 23 ex color subcarrier control 2 24 xx color subcarrier control 3 25 xx color subcarrier control 4 26 xx pixel delay control 27 58 manual clock control 1 28 xx manual clock control 2 29 xx manual clock control 3 2a xx auto clock control . 2b a0 agc mode control 2c ce chroma gain control 1 2d fx chroma gain control 2 2e xx luma gain control 1 2f fx luma gain control 2 30 xx manual gain shadow control 1 31 7x manual gain shadow control 2 32 xx miscellaneous gain control 33 e3 hsync position control 1 34 0f hsync position control 2 35 01 hsync position control 3 36 00 polarity control 37 00 reserved 44 x1 reserved 45 xx reserved f1 fx reserved f2 9x
rev. 0 ?38? ADV7185 appendix board design and layout considerations the ADV7185 is a highly integrated circuit containing both precision analog and high speed digital circuitry. it has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. it is impera- tive that these same design and layout techniques be applied to the system level design such that high speed and accurate per- formance are achieved. figure 30 shows the recommended analog circuit layout. the layout should be optimized for lowest noise on the ADV7185 power and ground lines by shielding the digital inputs and provid- ing good decoupling. the lead length between groups of vdd and gnd pins should be minimized to reduce inductive ringing. ground planes the ground plane should be split into two, one analog and one digital. they should be joined directly under the ADV7185. the analog ground return path should be through the digital (the digital ground is connected to the analog ground and also the system ground, whereas the analog ground is only con nected to the digital ground; this will ensure only analog current will flow in the analog ground). power planes the ADV7185 and any associated analog circuitry should have its own power planes, referred to as the analog and digital p ow er p lan es . these power planes should be connected to the regular pcb power plane (v cc ) at a single point through a ferrite bead. this bead should be located within three inches of the ADV7185. the pcb power plane should provide power to all digital logic on the pc board and the digital power pins on the adv 7185, and the analog power plane should provide power to all analog power pins on the ADV7185. plane-to-plane noise coupling can be reduced by ensuring that portions of the regular pcb power and ground planes do not overlay portions of the analog power plane, unless they can be arranged so the plane-to-plane noise is common-mode. supply decoupling for optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable opera tion, to reduce the lead inductance. best performance is obtained with 0.1
rev. 0 ADV7185 ?39? ain1 ain2 ain3 ain4 ain5 ain6 a vss avss a vss a vss a vss a vss 100nf 100nf 100nf 100nf 100nf 100nf ain1 ain2 ain3 ain4 ain5 ain6 a vss6 a vss5 a vss4 a vss3 a vss2 a vss1 dv ddio dvdd avdd gpo[0]/p0 p2 p4 p6 p8 gpo[2]/p10 gpo[3]/p11 p9 p7 p5 p3 gpo[1]/p1 p12 p14 p16 p18 p19 p17 p15 p13 dvdd ferrite bead 33 f 10 f d vss d vss av d d ferrite bead 33 f 10 f a vss a vss a vss d vss 0.1 f 0.01 f d vss d vss 0.1 f 0.01 f a vss a vss power supply decoupling for each power pin power supply decoupling for each power pin input switch over iso 10 f 0.1 f 0.1 f 0.1 f a vss a vss 10 f 0.1 f 0.1 f 0.1 f a vss a vss cap y1 cap y2 capc1 capc2 0.1 f cml refout 10 f 0.1 f a vss xtal xtal1 33 f 33 f 27mhz d vss d vss d vss dvdd alsb sclk sda reset i 2 c in terface control line i 2 c in terface control line 100r 100r 2k 2k dvdd dvdd 100nf d vss dvdd reset multiformat pixel port * p19ep12: 8-bit ccir656 pixel data @ 27mhz p19ep10: 10-bit extended ccir656 pixel data @ 27mhz p9ep2: cb and cr 16-bit ccir656 pixel data @ 13.5mhz p19ep12: y1 and y2 16-bit ccir656 pixel data @ 13.5mhz p9ep0: cb and cr 20-bit extended ccir656 pixel data @ 13.5mhz p19ep10: y1 and y2 20-bit extended ccir656 pixel data @ 13.5mhz * llc2 llcref llc aef rd dv gl/qclk/hff oe aff 27mhz output clock 13.5mhz output clock clock reference o/p almost empty fifo o/p almost full fifo o/p read signal i/p output enable i/p data va lid o/p gl/qclk/hff o/p vs/ reset field hs/ reset hs/ reset o/p vs/ reset o/p field o/p pwrdn power-down input fifo management signals only used in fifo mode; use llc and genlock for non-fifo mode elpf 5.6k 2nf 68pf av d d 4.7k figure 30. recommended analog circuit layout
c01677?0?5/02(0) printed in u.s.a. ?40? ADV7185 rev. 0 outline dimensions dimensions shown in millimeters and (inches) 80-lead thin plastic quad flatpack [lqfp] (st-80) top view (pins down) 1 20 21 41 40 60 61 80 16.25 (0.6398) 15.75 (0.6201) sq 14.05 (0.5532) 13.95 (0.5492) sq 0.35 (0.0138) 0.25 (0.0098) 0.73 (0.0287) 0.57 (0.0224) 12.35 (0.4862) typ sq 1.60 (0.0630) max 0.75 (0.0295) 0.50 (0.0197) seating plane 0.15 (0.0059) 0.05 (0.0020) 0.10 (0.0039) max 1.45 (0.0571) 1.35 (0.0531) coplanarity controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design

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